1. Field of the Invention.
The present invention applies to testing for the inspection and verification of the electrical operation of integrated circuits. The present invention is particularly aimed at the problem of applying electrical stimuli to and measuring the response from integrated circuits at precise and accurate time intervals.
2. The Prior Art
Modern integrated circuits are quite complex and to verify the proper operation of these devices it is necessary to apply electrical stimuli and measure the response with high accuracy and precision. It is customary in modern automatic test equipment (ATE) for integrated circuits to have a stabilized master oscillator from which all other timings are derived. A problem arises because it is often desired to generate signals at time intervals shorter than one period of the master oscillator. For example, the master oscillator might have a frequency of 100 MHz. Such an oscillator has a period of 10 nsec. However, in the tester it may be desired to place timing edges with precision of 25 psec and an accuracy of 100 psec. This is typically accomplished by using a delay line to form a timing vernier as is shown in the prior art. The signal passes through the delay line which has taps spaced closely apart in time. By selecting the appropriate taps several signals with intermediate timing can be generated. This procedure has been discussed in some detail by Nagy and by Herlein.
The prior art is primarily concerned with circuits implemented in emitter coupled logic (ECL). ECL is a current mode logic family used in bipolar integrated circuits. Because it is current mode logic, current is steered from one transistor to another. This logic family has the advantages that it is relatively fast and has constant power consumption because of the constant current flowing through the logic elements. Later versions of this logic (e.g. the 100k series) are temperature compensated. For these and perhaps other reasons such as the assumption that the ATE equipment would be used in carefully temperature controlled rooms, the prior art has not been concerned with compensating the delay lines for variation in environmental parameters such as power supply voltage and delay line temperature.
A difficulty with ECL logic is that the power consumption per logic gate is relatively high. This fact has inhibited the use of ECL for high levels of integration because the power consumption exceeds the limits of desirable packages. Fortunately as integrated circuit technology has progressed and demanded higher speed, more accurate and more complicated testing equipment (e.g. modern products have many more external signal connections than earlier products) it has also provided in CMOS technology a very high speed logic technology suitable to very high levels of integration.
One problem that must be overcome for CMOS technology to be applied to the timing vernier circuitry is that CMOS logic propagation delays are dependent upon the power supply voltage and the temperature of the silicon substrate. The supply voltage sensitivity can be managed by very tightly regulating the supply voltage; however this adds cost to the test system. The temperature of the substrate is much more difficult to control. If the power dissipation of a circuit is constant, the substrate temperature can be controlled by placing the circuit in a temperature controlled oven as has been known in the prior art for many years. In CMOS logic, the principal power dissipation is a result of capacitive charging and discharging; consequently, the power dissipation is approximately proportional to the square of the operating frequency. This means that if the circuit operating frequency were to suddenly increase, as it will in many common test modes, the power dissipation may easily increase by a factor of 100. This sudden burst of power is very difficult to account for with an oven.
On the other hand if a means of providing accurate and constant time delays could be provided with CMOS circuitry which is capable of operating over a wider range of environmental conditions, a tester could be fabricated that would not be restricted to rooms with carefully controlled environments, it could increase the utility of the tester just as the modern desktop computer is more flexible than its mainframe predecessor.
It is therefore an object of the present invention to provide a system and method for providing accurate and constant time delays utilizing CMOS circuitry.
It is a further object of the invention to provide a system and method for providing accurate and constant time delays utilizing CMOS circuitry which is capable of operating over a wider range of environmental conditions than heretofore possible.